BDD Based Procedures for a Theory of Equality with Uninterpreted Functions

Verification of RTL generated from scheduled behavior in a high-level synthesis flow

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

OBDD-based planning with real-valued variables in non-deterministic environments

AAAI '99/IAAI '99 Proceedings of the sixteenth national conference on Artificial intelligence and the eleventh Innovative applications of artificial intelligence conference innovative applications of artificial intelligence

Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction

Proceedings of the 37th Annual Design Automation Conference

Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

ACM Transactions on Computational Logic (TOCL)

Scalable hybrid verification of complex microprocessors

Proceedings of the 38th annual Design Automation Conference

Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW

Proceedings of the 38th annual Design Automation Conference

Boolean satisfiability with transitivity constraints

ACM Transactions on Computational Logic (TOCL)

Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function

Formal Methods in System Design

The small model property: how small can it be?

Information and Computation

Using BDDs with Combinations of Theories

LPAR '02 Proceedings of the 9th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning

Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

On Solving Presburger and Linear Arithmetic with SAT

FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design

Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors

TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems

Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic

CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions

TABLEAUX '99 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods

Deciding Equality Formulas by Small Domains Instantiations

CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification

EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations

CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification

Range Allocation for Equivalence Logic

FST TCS '01 Proceedings of the 21st Conference on Foundations of Software Technology and Theoretical Computer Science

Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions

CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification

Finite Instantiations in Equivalence Logic with Uninterpreted Functions

CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification

Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors

Journal of Symbolic Computation

Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Efficient formal verification of pipelined processors with instruction queues

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Efficient translation of boolean formulas to CNF in formal verification of microprocessors

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Using positive equality to prove liveness for pipelined microprocessors

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Building small equality graphs for deciding equality logic with uninterpreted functions

Information and Computation

Generalizing DPLL and satisfiability for equalities

Information and Computation

A New Approach for the Construction of Multiway Decision Graphs

Proceedings of the 5th international colloquium on Theoretical Aspects of Computing

EufDpll - A Tool to Check Satisfiability of Equality Logic Formulas

Electronic Notes in Theoretical Computer Science (ENTCS)

A Term Rewriting Technique for Decision Graphs

Electronic Notes in Theoretical Computer Science (ENTCS)

Building small equality graphs for deciding equality logic with uninterpreted functions

Information and Computation

Equational binary decision diagrams

LPAR'00 Proceedings of the 7th international conference on Logic for programming and automated reasoning

A method for debugging of pipelined processors in formal verification by correspondence checking

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors

ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering

Automatic formal verification of reconfigurable DSPs

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Computing small unsatisfiable cores in satisfiability modulo theories

Journal of Artificial Intelligence Research

A BDD-Representation for the logic of equality and uninterpreted functions

MFCS'05 Proceedings of the 30th international conference on Mathematical Foundations of Computer Science

Yet another decision procedure for equality logic

CAV'05 Proceedings of the 17th international conference on Computer Aided Verification

Automatic formal verification of liveness for pipelined processors with multicycle functional units

CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods