Proceedings of the 37th Annual Design Automation Conference
ACM Transactions on Computational Logic (TOCL)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A Comparison of Two Verification Methods for Speculative Instruction Execution
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verifying Advanced Microarchitectures that Support Speculation and Exceptions
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Microarchitecture Verification by Compositional Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Experience with Term Level Modeling and Verification of the M*Core microprocessor Core.
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Verifying Tomasulo's Algoithm by Refinement
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Proceedings of the conference on Design, automation and test in Europe
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
Proceedings of the 40th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Refinement strategies for verification methods based on datapath abstraction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Verification of executable pipelined machines with bit-level interfaces
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A complete compositional reasoning framework for the efficient verification of pipelined machines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Monolithic verification of deep pipelines with collapsed flushing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
The SAT-based Approach to Separation Logic
Journal of Automated Reasoning
Answer Set Programming Based on Propositional Satisfiability
Journal of Automated Reasoning
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SMT(CLU): a step toward scalability in system verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Predicate abstraction with indexed predicates
ACM Transactions on Computational Logic (TOCL)
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Challenge of Hardware-Software Co-verification
Verified Software: Theories, Tools, Experiments
Encoding Queues in Satisfiability Modulo Theories Based Bounded Model Checking
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Modelling and verification of superscalar Micro-architectures functional approach
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
A refinement-based compositional reasoning framework for pipelined machine verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TSAT++: an Open Platform for Satisfiability Modulo Theories
Electronic Notes in Theoretical Computer Science (ENTCS)
Verification of data paths using unbounded integers: automata strike back
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Optimization techniques for verification of out-of-order execution machines
Journal of Electrical and Computer Engineering
Property-specific sequential invariant extraction for SAT-based unbounded model checking
Proceedings of the International Conference on Computer-Aided Design
System description: Combination of Isabelle/HOL with automatic tools
FroCoS'05 Proceedings of the 5th international conference on Frontiers of Combining Systems
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Formal verification of infinite state systems using boolean methods
RTA'06 Proceedings of the 17th international conference on Term Rewriting and Applications
A progressive simplifier for satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
CPP'11 Proceedings of the First international conference on Certified Programs and Proofs
APLAS'11 Proceedings of the 9th Asian conference on Programming Languages and Systems
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatized high-level evaluation of security properties for RTL hardware designs
Proceedings of the Workshop on Embedded Systems Security
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In this paper, we describe the modeling and verification of out-of-order microprocessors with unbounded resources using an expressive, yet efficiently decidable, quantifier-free fragment of first order logic. This logic includes uninterpreted functions, equality, ordering, constrained lambda expressions, and counter arithmetic. UCLID is a tool for specifying and verifying systems expressed in this logic. The paper makes two main contributions. First, we show that the logic is expressive enough to model components found in most modern microprocessors, independent of their actual sizes. Second, we demonstrate UCLID's verification capabilities, ranging from full automation for bounded property checking to a high degree of automation in proving restricted classes of invariants. These techniques, coupled with a counterexample generation facility, are useful in establishing correctness of processor designs. We demonstrate UCLID's methods using a case study of a synthetic model of an out-of-order processor where all the invariants were proved automatically.