RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Automatically validating temporal safety properties of interfaces
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
The FSAP/NuSMV-SA Safety Analysis Platform
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on Advances in Automated Verification of Critical Systems
Formal verification of security specifications with common criteria
Proceedings of the 2007 ACM symposium on Applied computing
Industrial Use of Formal Methods for a High-Level Security Evaluation
FM '08 Proceedings of the 15th international symposium on Formal Methods
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
Combining fault injection and model checking to verify fault tolerance in multi-agent systems
Proceedings of The 8th International Conference on Autonomous Agents and Multiagent Systems - Volume 1
Formal security policy models for smart card evaluations
Proceedings of the 27th Annual ACM Symposium on Applied Computing
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The ever increasing integration of embedded systems into our every lives created a strong demand for trustable software and hardware implementations. To provide such trust between manufacturer and customer of integrated systems, regulatory rules like the Common Criteria have been defined. While this international standard clearly prescribes the usage of formal methods at high assurance level, formal verification at code-level is not widespread in practice. This work introduces a novel approach to verify the correct functionality of security critical hardware implementations under fault conditions. Generality is enabled by high-level evaluation using state machines extracted in an automatized way.