Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
Proceedings of the 37th Annual Design Automation Conference
A methodology for hardware verification using compositional model checking
Science of Computer Programming - Special issue on mathematics of program construction
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verifying Advanced Microarchitectures that Support Speculation and Exceptions
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Verifying Tomasulo's Algoithm by Refinement
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
An efficient algorithm for exploiting multiple arithmetic units
IBM Journal of Research and Development
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Local Proofs for Linear-Time Properties of Concurrent Programs
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Structured specifications for better verification of heap-manipulating programs
FM'11 Proceedings of the 17th international conference on Formal methods
Pipelined microprocessors optimization and debugging
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Formal Methods in System Design
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bounded satisfiability checking of metric temporal logic specifications
ACM Transactions on Software Engineering and Methodology (TOSEM) - In memoriam, fault detection and localization, formal methods, modeling and design
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Compositional model checking is used to verify a processor microarchitecture containing most of the features of a modern microprocessor, including branch prediction, speculative execution, out-of-order execution and a load-store buffer supporting re-ordering and load forwarding. We observe that the proof methodology scales well, in that the incremental proof cost of each feature is low. The proof is also quite concise with respect to proofs of similar microarchitecture models using other methods.