Handbook of formal languages, vol. 1
Journal of the ACM (JACM)
Efficient implementation of regular languages using reversed alternating finite automata
Theoretical Computer Science - Special issue on implementing automata
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
On Solving Presburger and Linear Arithmetic with SAT
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Efficient Implementation of Regular Languages Using R-AFA
WIA '97 Revised Papers from the Second International Workshop on Implementing Automata
A Comparison of Presburger Engines for EFSM Reachability
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Diophantine Equations, Presburger Arithmetic and Finite Automata
CAAP '96 Proceedings of the 21st International Colloquium on Trees in Algebra and Programming
Synthesis for unbounded bit-vector arithmetic
IJCAR'12 Proceedings of the 6th international joint conference on Automated Reasoning
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We present a decision procedure for quantifier-free Presburger arithmetic that is based on a polynomial time translation of Presburger formulas to alternating finite automata (AFAs).Moreover, our approach leverages the advances in SAT solving by reducing the emptiness problem of AFAs to satisfiability problems of propositional logic. In order to obtain a complete decision procedure, we use an inductive style of reasoning as originally proposed for proving safety properties in bounded model checking. Besides linear arithmetic constraints, our decision procedure can deal with bitvector operations that frequently occur in hardware design. Thus, it is well-suited for the verification of data paths at a high level of abstraction.