ACM Transactions on Computational Logic (TOCL)
Proceedings of the 38th annual Design Automation Conference
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Boolean Satisfiability with Transitivity Constraints
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Temporal-Safety Proofs for Systems Code
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Checking Satisfiability of First-Order Formulas by Incremental Translation to SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Deciding Separation Formulas with SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Structural search for RTL with predicate learning
Proceedings of the 42nd annual Design Automation Conference
RTL SAT simplification by Boolean and interval arithmetic reasoning
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Verification of executable pipelined machines with bit-level interfaces
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Predicate learning and selective theory deduction for a difference logic solver
Proceedings of the 43rd annual Design Automation Conference
MathSAT: Tight Integration of SAT and Mathematical Decision Procedures
Journal of Automated Reasoning
Propositional Satisfiability and Constraint Programming: A comparative survey
ACM Computing Surveys (CSUR)
Efficient theory combination via boolean search
Information and Computation - Special issue: Combining logical systems
A Quantifier-free First-order Knowledge Logic of Authentication
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
SMT(CLU): a step toward scalability in system verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Chain programming over difference constraints
Nordic Journal of Computing
An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
New results on rewrite-based satisfiability procedures
ACM Transactions on Computational Logic (TOCL)
Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT($\mathcal{LIA}$)
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Boolean satisfiability from theoretical hardness to practical success
Communications of the ACM - A Blind Person's Interaction with Technology
Optimal Length Resolution Refutations of Difference Constraint Systems
Journal of Automated Reasoning
Journal of Artificial Intelligence Research
Theory decision by decomposition
Journal of Symbolic Computation
Encoding RTL Constructs for MathSAT: a Preliminary Report
Electronic Notes in Theoretical Computer Science (ENTCS)
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Deciding separation logic formulae by SAT and incremental negative cycle elimination
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Optimizations for compiling declarative models into boolean formulas
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
The heuristic theorem prover: yet another SMT modulo theorem prover
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
An incremental and layered procedure for the satisfiability of linear arithmetic logic
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Efficient satisfiability modulo theories via delayed theory combination
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Decision procedures customized for formal verification
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
From propositional satisfiability to satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
SDSAT: tight integration of small domain encoding and lazy approaches in a separation logic solver
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
A Quantifier-free First-order Knowledge Logic of Authentication
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
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SAT-based decision procedures for quantifier-free fragments of first-order logic have proved to be useful in formal verification. These decision procedures are either based on encoding atomic subformulas with Boolean variables, or by encoding integer variables as bit-vectors. Based on evaluating these two encoding methods on a diverse set of hardware and software benchmarks, we conclude that neither method is robust to variations in formula characteristics. We therefore propose a new hybrid technique that combines the two methods. We give experimental results showing that the hybrid method can significantly outperform either approach as well as other decision procedures.