Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Model checking
A machine program for theorem-proving
Communications of the ACM
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Dynamic detection and removal of inactive clauses in SAT with application in image computation
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Checking Satisfiability of First-Order Formulas by Incremental Translation to SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
Proceedings of the 40th annual Design Automation Conference
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases
Proceedings of the 40th annual Design Automation Conference
Learning from BDDs in SAT-based bounded model checking
Proceedings of the 40th annual Design Automation Conference
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Model Checking C Programs Using F-SOFT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Deciding separation logic formulae by SAT and incremental negative cycle elimination
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
DiVer: SAT-based model checking platform for verifying large scale systems
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Symmetry reduction in SAT-based model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
F-SOFT: software verification platform
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
SDSAT: tight integration of small domain encoding and lazy approaches in a separation logic solver
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Managing SAT inconsistencies with HUMUS
Proceedings of the Sixth International Workshop on Variability Modeling of Software-Intensive Systems
A comparison of strategies for tolerating inconsistencies during decision-making
Proceedings of the 16th International Software Product Line Conference - Volume 1
FPGA acceleration of enhanced boolean constraint propagation for SAT solvers
Proceedings of the International Conference on Computer-Aided Design
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Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods. This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. We focus separately on methods for finding bugs and for finding proofs for correctness properties, along with highlighting the many common themes that benefit these methods. We also describe practical experiences with these methods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.