GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers
Proceedings of the 45th annual Design Automation Conference
The effect of restarts on the efficiency of clause learning
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Predicting learnt clauses quality in modern SAT solvers
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
A lightweight component caching scheme for satisfiability solvers
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
Designing an efficient hardware implication accelerator for SAT solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Relieving capacity limits on FPGA-based SAT-solvers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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We propose a hardware architecture to accelerate boolean constraint propagation (BCP). Although satisfiability (SAT) solvers in software use varying search and learning strategies, BCP is a fundamental component and by far consumes the most CPU time. Our field-programmable gate array (FPGA) design uses on-chip SRAM to facilitate the acceleration of BCP. We discuss many insights to our innovative hardware memory layout, which is very compact and enables extremely fast BCP. It also supports multithreading to minimize the idle time in hardware and to fully utilize the multicore processor host. Additionally, many industrial SAT instances encode logic gates as constraints. We compact these to simultaneously reduce the hardware memory usage as well as speed up the computation (enhanced BCP). We implemented our enhanced BCP core and integrated it with a simple software SAT solver which communicates over PCI Express. Hardware performance counters show that a single processing engine is up to 4x faster than a state-of-the-art software SAT solver.