Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
An Industrial Strength Theorem Prover for a Logic Based on Common Lisp
IEEE Transactions on Software Engineering
ACM Transactions on Computational Logic (TOCL)
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
Successive Approximation of Abstract Transition Relations
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Identifying conflicts in overconstrained temporal problems
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SMT(CLU): a step toward scalability in system verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reveal: A Formal Verification Tool for Verilog Designs
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Generalizing Core-Guided Max-SAT
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
Searching for autarkies to trim unsatisfiable clause sets
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Boosting minimal unsatisfiable core extraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Distilling critical attack graph surface iteratively through minimum-cost SAT solving
Proceedings of the 27th Annual Computer Security Applications Conference
Learning conditional abstractions
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Factoring out assumptions to speed up MUS extraction
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
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In this paper we explore the application of Counter example-Guided Abstraction Refinement (CEGAR) in the context of microprocessor correspondence checking. The approach utilizes automatic datapath abstraction, augmented with automatic refinement based on 1) localization, 2) generalization, and 3) minimal unsatisfiable subset (MUS) extraction. We introduce several refinement strategies and empirically evaluate their effectiveness on a set of microprocessor benchmarks. The data suggest that localization, generalization, and MUS extraction from both the abstract and concrete models are essential for effective verification. Additionally, refinement tends to converge faster when multiple MUses are extracted in each iteration.