Microprocessor design verification
Journal of Automated Reasoning
Machine Learning
BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Reconsidering CEGAR: Learning Good Abstractions without Refinement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Refinement strategies for verification methods based on datapath abstraction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Practical Approach to Word Level Model Checking of Industrial Netlists
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Computer Systems: A Programmer's Perspective
Computer Systems: A Programmer's Perspective
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Sciduction: combining induction, deduction, and structure for verification and synthesis
Proceedings of the 49th Annual Design Automation Conference
Learning-Based test programming for programmers
ISoLA'12 Proceedings of the 5th international conference on Leveraging Applications of Formal Methods, Verification and Validation: technologies for mastering change - Volume Part I
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Abstraction is central to formal verification. In term-level abstraction, the design is abstracted using a fragment of first-order logic with background theories, such as the theory of uninterpreted functions with equality. The main challenge in using term-level abstraction is determining what components to abstract and under what conditions. In this paper, we present an automatic technique to conditionally abstract register transfer level (RTL) hardware designs to the term level. Our approach is a layered approach that combines random simulation and machine learning inside a counter-example guided abstraction refinement (CEGAR) loop. First, random simulation is used to determine modules that are candidates for abstraction. Next, machine learning is used on the resulting simulation traces to generate candidate conditions under which those modules can be abstracted. Finally, a verifier is invoked. If spurious counterexamples arise, we refine the abstraction by performing a further iteration of random simulation and machine learning. We present an experimental evaluation on processor designs.