Compressing BMC Encodings with QBF
Electronic Notes in Theoretical Computer Science (ENTCS)
Semi-external LTL Model Checking
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Solving μ-Calculus Parity Games by Symbolic Planning
Model Checking and Artificial Intelligence
Survey on Directed Model Checking
Model Checking and Artificial Intelligence
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Model-based Runtime Verification Framework
Electronic Notes in Theoretical Computer Science (ENTCS)
Termination Criteria for Bounded Model Checking: Extensions and Comparison
Electronic Notes in Theoretical Computer Science (ENTCS)
Liveness Checking as Safety Checking for Infinite State Spaces
Electronic Notes in Theoretical Computer Science (ENTCS)
Language-Emptiness Checking of Alternating Tree Automata Using Symbolic Reachability Analysis
Electronic Notes in Theoretical Computer Science (ENTCS)
I/O efficient accepting cycle detection
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Revisiting resistance speeds up I/O-efficient LTL model checking
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Scalable formula decomposition for propositional satisfiability
Proceedings of the Third C* Conference on Computer Science and Software Engineering
Flash memory efficient LTL model checking
Science of Computer Programming
External memory breadth-first search with delayed duplicate detection on the GPU
MoChArt'10 Proceedings of the 6th international conference on Model checking and artificial intelligence
Shortest counterexamples for symbolic model checking of LTL with past
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
An incremental approach to model checking progress properties
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Proving ∀µ-calculus properties with SAT-based model checking
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Computing infinite plans for LTL goals using a classical planner
IJCAI'11 Proceedings of the Twenty-Second international joint conference on Artificial Intelligence - Volume Volume Three
Parallel model checking using abstraction
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
Scalable progress verification in credit-based flow-control systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A symbolic model checking approach to verifying satellite onboard software
Science of Computer Programming
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Two types of temporal properties are usually distinguished: safety and liveness. Recently we have shown how to verify liveness properties of finite state systems using safety checking. In this article we extend the translation scheme to typical combinations of temporal operators. We discuss optimizations that limit the overhead of our translation. Using the notions of predicated diameter and radius we obtain revised bounds for our translation scheme. These notions also give a tight bound on the minimal completeness bound for simple liveness properties. Experimental results show the feasibility of the approach for complex examples. For one example, even an exponential speedup can be observed.