Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Testing language containment for &ohgr;-automata using BDDs
Information and Computation
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
Analysis of Symbolic SCC Hull Algorithms
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Divide and Compose: SCC Refinement for Language Emptiness
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Efficient reduction of finite state model checking to reachability analysis
International Journal on Software Tools for Technology Transfer (STTT)
Fate and free will in error traces
International Journal on Software Tools for Technology Transfer (STTT) - Special section on tools and algorithms for the construction and analysis of systems
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
Formal Methods in System Design
Checking Safety by Inductive Generalization of Counterexamples to Induction
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Termination Criteria for Bounded Model Checking: Extensions and Comparison
Electronic Notes in Theoretical Computer Science (ENTCS)
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Implicit enumeration of strongly connected components and an application to formal verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IC3: where monolithic and incremental meet
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
IC3 and beyond: incremental, inductive verification
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Software model checking via IC3
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Incremental, inductive CTL model checking
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
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An incremental algorithm for model checking progress properties is proposed. It follows from the following insight: any SCC-closed region of a system's state graph can be represented by a sequence of inductive assertions. Each iteration of the algorithm selects a set of states, called a skeleton, that together satisfy all fairness conditions; it then applies safety model checkers to attempt to connect the states into a reachable fair cycle. If this attempt fails, the resulting learned lemma takes one of two forms: an inductive reachability assertion that shows that at least one state of the skeleton is unreachable, or an inductive wall that defines two SCC-closed regions of the state graph. Subsequent skeletons must be chosen entirely from one side of the wall. Because a lemma often applies more generally than to the one skeleton from which it was derived, property-directed abstraction is achieved. The algorithm is highly parallelizable.