AND/OR graph heuristic search methods
Journal of the ACM (JACM)
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Principles of artificial intelligence
Principles of artificial intelligence
Alternating automata on infinite trees
Theoretical Computer Science
Handbook of theoretical computer science (vol. B)
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
Model checking
An automata-theoretic approach to branching-time model checking
Journal of the ACM (JACM)
Directed explicit model checking with HSF-SPIN
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Symbolic Model Checking
Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Heuristic Search + Local Model Checking in Selective mu-Calculus
IEEE Transactions on Software Engineering
Efficient reduction of finite state model checking to reachability analysis
International Journal on Software Tools for Technology Transfer (STTT)
Model Checking Temporal-Epistemic Logic Using Alternating Tree Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
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Alternating tree automata and AND/OR graphs provide elegant formalisms that enable branching- time logics to be verified in linear time. The seminal work of Kupferman et al. [Orna Kupferman, Moshe Y. Vardi, and Pierre Wolper. An automata-theoretic approach to branching-time model checking. J. ACM, 47(2):312-360, 2000] showed that 1) branching-time model checking is reducible to the language non-emptiness checking of the product of two alternating automata representing the model and property under verification, and 2) the non-emptiness problem can be solved by performing a search on an AND/OR graph representing this product. Their algorithm, however, can only be implemented in an explicit-state model checker because it needs stacks to detect accept and reject runs. In this paper, we propose a BDD-based approach to check the language non-emptiness of the product automaton. We use a technique called ''state recording'' from Schuppan and Biere [Viktor Schuppan and Armin Biere. Efficient reduction of finite state model checking to reachability analysis. Int. Journal on Software Tools for Technology Transfer (STTT), 5(2-3):185-204, 2004] to emulate the stack mechanism from explicit-state model checking. This technique allows us to transform the product automaton into a well-defined AND/OR graph. We develop a BDD-based reachability algorithm to efficiently determine whether a solution graph for the AND/OR graph exists and thereby solve the model-checking problem. While ''state recording'' increases the size of the state space, the advantage of our approach lies in the memory saving BDDs can offer and the potential it opens up for optimisation of the reachability analysis. We remark that this technique always detects the shortest counter-example.