Overview of complementary GaAs technology for high-speed VLSI circuits

  • Authors:

  • Richard B. Brown;Bruce Bernhardt;Mike LaMacchia;Jon Abrokwah;Phiroze N. Parakh;Todd D. Basso;Spencer M. Gold;Sean Stetson;Claude R. Gauthier;David Foster;Brian Crawforth;Timothy McQuire;Karem Sakallah;Ronald J. Lomax;Trevor N. Mudge

  • Affiliations:

  • Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Motorola, Semiconductor Products Sector, Tempe, AZ;Motorola, Space and Systems Technology Group, Scottsdale, AZ;Motorola, Phoenix Corporate Research Laboratories, Tempe, AZ;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Motorola, Space and Systems Technology Group, Scottsdale, AZ;Motorola, Space and Systems Technology Group, Scottsdale, AZ;Motorola, Space and Systems Technology Group, Scottsdale, AZ;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 1998

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Abstract

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9V have demonstrated power-delay products of 0.01 µW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor.