Two-level adaptive training branch prediction
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Economy-class ion-defying ICs in orbit
IEEE Spectrum
A Quantitative Approach to Nonlinear Process Design Rule Scaling
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Overview of complementary GaAs technology for high-speed VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
uComplexity: Estimating Processor Design Effort
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
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The development of a PowerPC™ fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorola's 0.5—µm Complementary Gallium Arsenide process, the device operates from 0.9 to 1.9 V with a nominal frequency of 25 MHz at 1.3 V, dissipating 274 mW.