The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Peopleware (2nd ed.): productive projects and teams
Peopleware (2nd ed.): productive projects and teams
METRICS: a system architecture for design process optimization
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Software Engineering Economics
Software Engineering Economics
Metrics for structural logic synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Early estimation of the size of VHDL projects
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Fairness and Throughput in Switch on Event Multithreading
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Coherence Ordering for Ring-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Fairness enforcement in switch on event multithreading
ACM Transactions on Architecture and Code Optimization (TACO)
A performance-correctness explicitly-decoupled architecture
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Releasing efficient beta cores to market early
Proceedings of the 38th annual international symposium on Computer architecture
Productivity reanalysis for unbalanced datasets with mixed-effects models
PROFES'10 Proceedings of the 11th international conference on Product-Focused Software Process Improvement
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
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Microprocessor design complexity is growing rapidly. As a result, current development costs for top of the line processors are staggering, and are doubling every 4 years. As we design ever larger and more complex processors, it is becoming increasingly difficult to estimate how much time it will take to design and verify them. To compound this problem, processor design cost estimation still does not have a quantitative approach. Although designing a processor is very resource consuming, there is little work measuring, understanding, and estimating the effort required. To address this problem, this paper introduces µComplexity, a methodology to measure and estimate processor design effort. µComplexity consists of three main parts, namely a procedure to account for the contributions of the different components in the design, accurate statistical regression of experimental measures using a nonlinear mixed-effects model, and a productivity adjustment to account for the productivities of different teams. We use µComplexity to evaluate a series of design effort estimators on several processor designs. Our analysis shows that the number of lines of HDL code, the sum of the fan-ins of the logic cones in the design, and a linear combination of the two metrics are good design effort estimators. On the other hand, power, area, frequency, number of flip-flops, and number of standard cells are poor estimators of design effort. We also show that productivity adjustments are necessary to produce accurate estimations.