High-Level Synthesis with Variable-Latency Components
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
uComplexity: Estimating Processor Design Effort
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Introduction to High-Level Synthesis
IEEE Design & Test
Bridging the domains of high-level and logic synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work provides new perspectives on impact of design effort, consumed resources and design abstraction on hardware performance in a high-level synthesis flow. We have shown that counter to published literature as well as intuition; more design effort may not always result in better performance. We developed a kernel that simulates Brownian motion, and investigated improvement in hardware performance with design effort at various abstraction levels. Our results indicate that a designer should be careful in putting more effort at a particular abstraction level. In our case, we achieved best performance/effort ratio at algorithm level rather than lower abstraction levels. This strongly suggests that design effort is not always proportional to corresponding improvement in performance.