Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents techniques to integrate the use of variable-latency units in a high-level synthesis design methodology. Components used as building blocks (e.g., functional units) in conventional high-level synthesis techniques are assumed to have fixed-latency values. Variable-latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on the input values. While variable-latency units offer potential for performance improvement, we demonstrate that realization of this potential requires that high-level synthesis be adapted suitably (sub-optimal use of variable-latency units can lead to performance degradation, or unnecessarily high area overheads).Our techniques to incorporate variable-latency units into high-level synthesis ensure that the performance improvement is maximized, while minimizing area overheads or satisfying resource constraints. These techniques are not restricted to specific high-level synthesis tools/algorithms, and can be plugged in to any generic high-level synthesis system. Since area overheads may still be incurred due to the use of variable-latency units, we present a novel technique, based on the concept of reduced variable-latency units, to further reduce area overheads. Reduced variable-latency units only implement the low-latency case behavior of complete variable-latency units. We demonstrate that the use of reduced variable-latency units significantly reduces area overheads, and frequently results in RTL implementations with simultaneous area and performance improvements} compared to fixed-latency implementations.Experimental results show that the proposed variable-latency unit based synthesis techniques achieve a performance improvement of up to 1.6X (average of 1.4X) over a state-of-the-art high-level synthesis tool, with minimal area overheads (average of 5.3%). The use of reduced variable-latency units leads to a performance improvement of up to 1.6X (average of 1.3X), with a simultaneous area reduction of up to 17.9% (10.6% on the average).