Design for manufacturability and yield
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
VLSI Design for Manufacturing: Yield Enhancement
VLSI Design for Manufacturing: Yield Enhancement
Overview of complementary GaAs technology for high-speed VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 37th Annual Design Automation Conference
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This paper describes a quantitative methodology for selecting nonlinear design rule scale factors that provide the most cost-efficient improvements in IC performance and area. The methodology includes identifying the design rules which have the greatest impact on the scaling objective and analyzing the area and performance improvements as these rules are scaled through a range of practical scale factors. Power and delay improvement data is then combined with die cost estimates to produce a cost/benefit ratio, a quantitative metric for design rule scaling cost-efficiency. The slopes and inflection points of cost/benefit vs. scale factor plots will guide process engineers in selecting scale factors for the various design rules. This procedure is repeated, using the results of one iteration as the starting point for the next.The cost/benefit analysis methodology is demonstrated by comparing embedded static RAMs implemented in a complementary GaAs (CGaAs TM ) process. The SRAMs are generated by a process-independent, optimizing SRAM compiler which can create SRAM macrocells for any complementary technology. A cost/benefit analysis of the CGaAs design rules shows that when operating under a fixed spending cap for process scaling research, development, and capital equipment acquisition, nonlinear scaling can provide greater improvements in area and performance than linear scaling. The results also show that for a 0.5-mm CGaAs process to be fabricated in high volume, the first scaling step should be a 30% reduction of the source drain area and via/metal pitch, gate metal to ohmic spacing, and gate metal spacing design rules.