Design verification considering manufacturing tolerances by using worst-caste distances
EURO-DAC '92 Proceedings of the conference on European design automation
Improved methods for worst-case analysis and optimization incorporating operating tolerances
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance driven global routing and wiring rule generation for high speed PCBs and MCMs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
How ATE Planning Affects LSI Manufacturing Cost
IEEE Design & Test
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
A Quantitative Approach to Nonlinear Process Design Rule Scaling
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Performance Improvement for High Speed Devices Using E-tests and the SPICE Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Yield optimization for radio frequency receiver at system level
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |