VLSI Design for Manufacturing: Yield Enhancement
VLSI Design for Manufacturing: Yield Enhancement
Analog Design Centering and Sizing
Analog Design Centering and Sizing
Efficient reliability simulation of analog ICs including variability and time-varying stress
Proceedings of the Conference on Design, Automation and Test in Europe
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper is devoted to the yield optimization of the radio-frequency (RF) front-end of wireless receiver. The yield together with the circuit performances are often sensitive to the choice of parameters of its components and blocks, and can be improved at circuit design level. However, it is better evaluated when considering the whole receiver at system level. For this purpose, we first use a design of experiment (DoE) technique to generate meta-models of the building blocks. Then, we apply a version of the stochastic gradient method to find a good approximation of the optimum for the circuit yield.