Emerging yield and reliability challenges in nanometer CMOS technologies
Proceedings of the conference on Design, automation and test in Europe
Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient variability-aware NBTI and hot carrier circuit reliability analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design automation towards reliable analog integrated circuits
Proceedings of the International Conference on Computer-Aided Design
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS
Proceedings of the Conference on Design, Automation and Test in Europe
Yield optimization for radio frequency receiver at system level
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Aggressive scaling to nanometer CMOS technologies causes both analog and digital circuit parameters to degrade over time due to die-level stress effects (i.e. NBTI, HCI, TDDB, etc). In addition, failure-time dispersion increases due to increasing process variability. In this paper an innovative methodology to simulate analog circuit reliability is presented. Advantages over current state of the art reliability simulators include, among others, the possibility to estimate the impact of variability and the ability to account for the effects of complex time-varying stress signals. Results show that taking time-varying stress signals into account provides circuit reliability information not visible with classic DC-only reliability simulators. Also, variability-aware reliability simulation results indicate a significant percentage of early circuit failures compared to failure-time results based on nominal design only.