Design For Degradation: CAD Tools for Managing Transistor Degradation Mechanisms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Very large fractional factorial and central composite designs
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Design and Analysis of Experiments
Design and Analysis of Experiments
Emerging yield and reliability challenges in nanometer CMOS technologies
Proceedings of the conference on Design, automation and test in Europe
Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient reliability simulation of analog ICs including variability and time-varying stress
Proceedings of the Conference on Design, Automation and Test in Europe
Analytical yield prediction considering leakage/performance correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design automation towards reliable analog integrated circuits
Proceedings of the International Conference on Computer-Aided Design
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS
Proceedings of the Conference on Design, Automation and Test in Europe
ITRS 2011 analog EDA challenges and approaches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction between process variability effects and circuit aging is introduced. This method is based on a screening experimental design (DoE) succeeded by a set of regression DoEs, resulting in a good speed-accuracy tradeoff with a nearly linear complexity for all circuits under test. Finally, based on the DoE analysis, a circuit response surface model (RSM) is derived. The RSM is used for further circuit reliability analysis such as circuit weak spot detection and yield calculation as a function of circuit lifetime. The proposed method is validated over a broad range of both analog and digital circuits. Yield simulation time is reduced with up to three orders of magnitude, when compared to standard Monte Carlo-based techniques and while still maintaining simulation accuracy.