Integrated placement for mixed macro cell and standard cell designs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
POSE: power optimization and synthesis environment
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A global routing algorithm for general cells
DAC '84 Proceedings of the 21st Design Automation Conference
Issues in Partitioning Integrated Circuits for MCM-D/Flip-Chip Technology
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Development of a DSP/MCM Subsystem Assessing Low-Volume, Low-Cost MCM Prototyping for Universities
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Design Implementation of Intrinsic Area Array ICs
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Area I/O Flip-Chip Packaging to Minimize Interconnect Length
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overview of complementary GaAs technology for high-speed VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cluster based dynamic area-array I/O planning for flip chip technology
Microelectronic Engineering
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The use of area interconnect packaging in high frequency microprocessors is motivated by its high-bandwidth and good power distribution capability. An MCM packaging scheme based on area-distributed I/O pads serves as the foundation of the PUMA project at the University of Michigan. Area interconnect facilitates high I/O counts, shorter interconnect routes, smaller power rails, and better thermal conductivity, all of which are important in high clock-rate digital systems. This paper introduces recently developed CAD tools that aid in the design of flip-chip area-interconnected integrated circuits. The tools permit the designer to place and route area bond pads as dictated by the layout of the microprocessor. System level issues, such as adequate power distribution and placement of area pad buffers, are addressed. The CAD system includes area pad power analysis, floorplanning, and routing tools.