Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
Design of FPGAs with area I/O for field programmable MCM
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Evolutionary Algorithms in Engineering Applications
Evolutionary Algorithms in Engineering Applications
Efficient circuit clustering for area and power reduction in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
I/O Pad Assignment Based on the Circuit Structure
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design of ICs for Flip-Chip Integration with Optoelectronic Device Arrays
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
CAD Tools for Area-Distributed I/O Pad Packaging
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Implications of Area-Array I/O for Row-Based Placement Methodology
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hypergraph partitioning with fixed vertices [VLSI CAD]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the recent advances in chip fabrication and the ever increasing demand for high performance circuits, the conventional peripheral I/O placement techniques fail to meet the stringent requirements of the chip design. As a result, the existing algorithms result in excessive wire length, long critical paths, and computationally expensive and intensive. In this paper we introduce a new area I/O placement technique that co-designs the chip and package. The present algorithm is non-iterative and constructive. It assigns the functional blocks and primary inputs/outputs simultaneously and considers the package imposed constraints during the planning stage. The algorithm progresses in stages. At each stage, the functional blocks are placed on the chip on the fly and grouped together to form clusters. Various criteria like primary input net span and adjacency of clusters are taken into consideration for the placement of functional blocks. Experimental results showed that due to the non-iterative property, the proposed algorithm achieved 10x speedup over the traditional algorithms while obtaining a planning solution with optimal wire length and minimized delay.