Design and evaluation of a photonic FFT processor
Journal of Parallel and Distributed Computing - Special issue on parallel computing with optical interconnects
Design of a 64-bit, 100 MIPS microprocessor core IC for hybrid CMOS-SEED technology
MPPOI '96 Proceedings of the 3rd Conference on Massively Parallel Processing Using Optical Interconnections
The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM
MPPOI '96 Proceedings of the 3rd Conference on Massively Parallel Processing Using Optical Interconnections
Design Implementation of Intrinsic Area Array ICs
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Cluster based dynamic area-array I/O planning for flip chip technology
Microelectronic Engineering
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Hybrid integration of optoelectronic devices, such as GaAs MQW modulators, to CMOS VLSI circuits provides the opportunity to design ICs that integrate millions of transistors and thousands of high-speed optical I/Os for high-performance computing and switching applications. One of the challenges in designing such large-scale ICs lies in the development of an efficient method for integrating existing VLSI circuit layouts with two-dimensional arrays of optoelectronic devices. This paper presents several such methods and describes their application.