Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits
The Journal of Supercomputing
Design of ICs for Flip-Chip Integration with Optoelectronic Device Arrays
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
| Hi-index | 0.00 |
We describe the design of a hybrid CMOS-SEED 64-bit microprocessor core IC with 192 optical I/Os. This 3.5 mm/sup 2/ IC was fabricated and electrically tested at 100 MHz with a performance of 100 million 64-bit instructions per second (MIPS). The processor design includes a 64-bit arithmetic-logic unit (ALU) which implements 16 logic and 32 fixed-point arithmetic functions. A 1 cm/sup 2/ chip can integrate thirty two 64-bit processors and achieve 3,200 64-bit MIPS. Further performance improvements can be achieved using improved processor architecture and/or a more advanced CMOS process. When combined with an appropriate photonic page buffer IC operating as a cache memory, it becomes possible to build a compact, two-chip parallel processor system.