Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
An interactive maze router with hints
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Design of ICs for Flip-Chip Integration with Optoelectronic Device Arrays
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
CAD Tools for Area-Distributed I/O Pad Packaging
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Intrinsic Area Array ICs: What, Why, and How?
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
An Obstacle-Avoiding Router for Custom VLSI
An Obstacle-Avoiding Router for Custom VLSI
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Arranging I/O in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/O than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. This method was pioneered by IBM over thirty years ago and has recently become attractive for new designs requiring several hundred I/O. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design guideline definition, data preparation, pad placement, pad assignment, pad routing, and output padframe generation of this technique. The results of applying this router are shown for sample designs requiring 112, 298 and 485 I/O.