High-performance physical design in multilayer packages
High-performance physical design in multilayer packages
An interactive maze router with hints
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An Obstacle-Avoiding Router for Custom VLSI
An Obstacle-Avoiding Router for Custom VLSI
SINGLE-LAYER FANOUT ROUTING AND ROUTABILITY ANALYSIS FOR BALL GRID ARRAYS
SINGLE-LAYER FANOUT ROUTING AND ROUTABILITY ANALYSIS FOR BALL GRID ARRAYS
Reliability of controlled collapse interconnections
IBM Journal of Research and Development
Thermal conduction module: a high-performance multilayer ceramic package
IBM Journal of Research and Development
Design Implementation of Intrinsic Area Array ICs
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Determination of Area-Array Bond Pitch for Optimum MCM Systems: A Case Study
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Modeling and design for beyond-the-die power integrity
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
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Area-array bonding technology (i.e. flip-chip, C4) was pioneered by IBM in the late 1960's as an alternative to periphery bonding technology (i.e. wire-bond). In recent years, several commercial companies have started offering bumping and flip-chip services. Flip-chip technology is expected to grow at at compound annual growth rate of 38% through the year 2001. The purpose of this paper is to address the IC design issues and alternatives that are presently being used for area-array bonding technology and show the impact of these design issues at the system level.