Implications of Area-Array I/O for Row-Based Placement Methodology

Implementation and extensibility of an analytic placer

Proceedings of the 2004 international symposium on Physical design

Post-Placement Pin Optimiztion

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design

Constraint driven I/O planning and placement for chip-package co-design

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Design migration from peripheral ASIC design to area-I/O flip-chip design by chip I/O planning and legalization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-in-Package: Electrical and Layout Perspectives

Foundations and Trends in Electronic Design Automation

A study of row-based area-array I/O design planning in concurrent chip-package design flow

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Cluster based dynamic area-array I/O planning for flip chip technology

Microelectronic Engineering