Introduction to algorithms
A new approach to the pin assignment problem
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
I/O Pad Assignment Based on the Circuit Structure
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Implications of Area-Array I/O for Row-Based Placement Methodology
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
Proceedings of the 2004 international symposium on Physical design
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Pin assignment is the process of placing pins on the boundary of a chip or macro during chip design. Problem is that cell placement and pin assignment form a chicken and egg problem: cell placement needs pin positions, while pin positions should be optimally adapted to the placement of cells. The contributions of this paper are threefold. First, the chicken and egg problem is tackled using the observation that pin positions mainly influence cell positions on the periphery of the circuit. A first placement run is used to place the "core" of the circuit followed by adapting pin positions such that wire length of the periphery of the circuit can be optimized. The second contribution is that pin assignment issues that arise in a hierarchical flow, where pins serve as connections between two hierarchical levels, can be incorporated. The final contribution is that the tedious process of manual "fiddling around" with pins in order to reduce congestion is automated through pin constraints set by the designer. Experimental evidence on a large benchmark suite with large designs shows that our method is effective. On average a significant 2.55% reduction in total wire length is achieved. For congested designs, such a reduction can make the difference between routable and not routable. This reduction is due to actual restructuring of the placement, showing the validity of the assumptions. The proposed methods are easily incorporated in common physical design flows.