Fastpath: A Path-Delay Test Generator for Standard Scan Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On Multiple Path Propagating Tests for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
Proceedings of the IEEE International Test Conference 2001
Test generation for crosstalk-induced faults: framework and computational results
ATS '00 Proceedings of the 9th Asian Test Symposium
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits
ATS '97 Proceedings of the 6th Asian Test Symposium
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Selection of Crosstalk-Induced Faults in Enhanced Delay Test
Journal of Electronic Testing: Theory and Applications
Non-robust Test Generation for Crosstalk-Induced Delay Faults
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Robust Test Generation for Precise Crosstalk-induced Path Delay Faults
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits
International Journal of Computer Applications in Technology
Cluster based dynamic area-array I/O planning for flip chip technology
Microelectronic Engineering
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In this paper, we propose a new test-generation method for delay faults considering crosstalk-induced delay effects, based on a conventional delay automatic-test-pattern-generation (ATPG) technique in order to reduce the complexity of previous ATPG algorithms and to consider multiple-aggressor crosstalk faults to maximize the noise of the victim line. Since the proposed ATPG for crosstalk-induced delay faults uses physical and timing information, it can reduce the search space of the backward implication of the aggressor's constraints, and it is helpful for reducing the ATPG time cost compared to previous works. In addition, since the proposed technique targets the critical path for the original delay test as the victim lines, it can improve test effectiveness of delay testing. Experimental results demonstrate the effectiveness of the proposed method.