SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different marginality issues that may render a circuit nonoperational. Capacitive cross coupling between interconnects is known to be a leading cause for marginality-related failures. In this paper, we present novel techniques to model and prioritize capacitive crosstalk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on large industrial designs.