On path selection in combinational logic circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Crosstalk noise in future digital CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
An evaluation of bipartitioning techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Constructing Current-Based Gate Models Based on Existing Timing Library
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe
Critical Path Selection for Delay Test Considering Coupling Noise
ETS '08 Proceedings of the 2008 13th European Test Symposium
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
An improved soft-error rate measurement technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Crosstalk faults have emerged as a significant mechanism of circuit failure due to decreasing process geometries and increasing operation frequencies. Long signal nets are highly susceptible to crosstalk faults because they tend to have a higher coupling capacitance to overall capacitance ratio. Moreover, a typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk induced delay on a victim net, it may be impossible to activate all aggressors logically or simultaneously to constructively induce maximum noise at the victim. Therefore, pattern generation must focus on activating a maximal subset of aggressors, weighted by actual coupling capacitance value, in close temporal proximity of the victim net transition. This max-satisfiability problem is constrained by fault effect propagation condition which involves determining an input signal assignment so as to propagate the fault effect at the victim to the primary output. In this paper, we present Automatic Test Pattern Generation (ATPG) solutions for multiple aggressor crosstalk faults for zero and unit delay models and compare the magnitude of crosstalk induced delay at the victim net. Our solution involves a combination of 0-1 Integer Linear Programming (ILP), for maximal aggressor excitation. Fault effect propagation is solved independently by using traditional stuckat fault ATPG or by generating additional ILP constraints thus forming a integrated ILP formulation with error propagation. The effect of gate delays is summed by circuit transformation. The proposed technique was applied to ISCAS85 benchmark circuits. Results indicate that the percentage of total capacitance that can be switched varies from 75-100% for zero delay and 30-80% for variable delay case while achieving propagation of the fault effect to primary output.