Timing Arc Based Logic Analysis for false noise reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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Identifying the set of real critical paths of a circuit is an important step in delay testing. Since path delays are vector dependent, the set of critical paths selected dependson the vectors assumed when estimating the path delays. To find the real critical paths, it is important to consider the effect of dynamic (vector dependent) delay effects such as coupling noise,supply noise etc. during path selection. In this work a methodology to incorporate the effect of coupling noise during path selection is described. For any given path, both logic and timing constraints are extracted and a constrained optimization problem is formulated to estimate the maximum path delay in the presence of coupling noise.