Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Generation of Hazard Identification Functions
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
False-Noise Analysis for Domino Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Delay noise pessimism reduction by logic correlations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Critical Path Selection for Delay Test Considering Coupling Noise
ETS '08 Proceedings of the 2008 13th European Test Symposium
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Eliminating false positives in crosstalk noise analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
False coupling exploration in timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it still lacks an efficient solution. As a result, state-of-the-art crosstalk calculators use simplistic and overly pessimistic models resulting in the over-estimation of crosstalk effects. Such pessimism in crosstalk analysis often leads to the triggering of false violations and consequently an inefficient use of design resources. The main contribution of this paper is a novel technique called Timing Arc Based Logic Analysis (TABLA) that serves as an efficient means to calculate realistic crosstalk bounds. TABLA uses timing arcs as basic elements to perform an efficient temporal logic analysis employing the min-max timing model using dedicated solvers for logic and timing. Additionally, a procedure to generate powerful conflict clauses is proposed to improve the run time of the overall analysis. The proposed technique has been tested in an industrial environment on benchmark circuits as well as on an industrial design, and results are provided.