Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Machine-Oriented Logic Based on the Resolution Principle
Journal of the ACM (JACM)
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
False-noise analysis using logic implications
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
False-Noise Analysis using Resolution Method
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing Arc Based Logic Analysis for false noise reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
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High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, producing the worst-case noise. However, due to logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Some techniques for computing logiccorrelations have been designed targeting static CMOS circuits. However high performance microprocessors commonly use domino logic for their ALU. The domino circuits have lower noise margins than static CMOS circuits and are more sensitive to coupled noise. Any unnecessary pessimism of the noise analysis tool results in large number of false noise violations and either requires additional extensive SPICE simulations or circuit over-design. Unfortunately false noise analysis developed for static CMOS circuits [11] fails to compute many logic correlations in domino circuits. In this paper we propose a novel technique of computing logic correlations in domino circuits. It takes into account the fact that both pull up and pull down networks of a domino gate can be in non conducting state. The proposed technique generates additional logic correlations for such states of domino gates. In order toimprove the capability of logic correlation derivation technique we combine the resolution method with recursive learning algorithm [12]. The proposed technique is implemented in an industrial noise analysis tool and tested on high performance ALU blocks.