Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
False-Noise Analysis for Domino Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Delay noise pessimism reduction by logic correlations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, thereby producing the worst-case noise on a net. However, due to the logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Since the problem has been shown to be NP-hard in general, exact solutions to this problem are not possible. In this paper, we therefore propose a new heuristic to eliminate false noise failures based on the resolution method. It is shown that multi-variable logic relations can be computed directly from a transistor level description. Based on these generated logic relations, a characteristic ROBDD for a signal net and its neighboring nets is constructed. This ROBDD is then used to determine the set of neighboring nets that result in the maximum realizable noise on the net. The proposed approach was implemented and tested on industrial circuits. The results demonstrate the effectiveness of the approach to eliminate false noise failures.