PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Efficient Crosstalk Estimation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Early probabilistic noise estimation for capacitively coupled interconnects
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Estimation of the likelihood of capacitive coupling noise
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
False-noise analysis using logic implications
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Estimation of signal arrival times in the presence of delay noise
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Temporofunctional crosstalk noise analysis
Proceedings of the 40th annual Design Automation Conference
Static noise analysis with noise windows
Proceedings of the 40th annual Design Automation Conference
Post-route gate sizing for crosstalk noise reduction
Proceedings of the 40th annual Design Automation Conference
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
False-Noise Analysis for Domino Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Eliminating False Positives in Crosstalk Noise Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Noise characterization of static CMOS gates
Proceedings of the 41st annual Design Automation Conference
SOI Transistor Model for Fast Transient Simulation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A complete methodology for an accurate static noise analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Analytical modeling of crosstalk noise waveforms using Weibull function
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Delay noise pessimism reduction by logic correlations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A non-iterative continuous model for switching window computation with crosstalk noise
Microelectronic Engineering
Top-k aggressors sets in delay noise analysis
Proceedings of the 44th annual Design Automation Conference
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
Victim alignment in crosstalk-aware timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Built-in sensor for signal integrity faults in digital interconnect signals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Receiver modeling for static functional crosstalk analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Crosstalk waveform modeling using wave fitting
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor design issues which have received limited discussion in the past. First, we present how the driver gates of a coupled interconnect network are represented with accurate linear models. Second, we show how to speed the analysis of large designs by using noise filters based on reduced interconnect representations and then pruning the nets coupled to a signal net. Third, we show how to incorporate logic and timing correlations into noise analysis to reduce its pessimism. We present the results from several industrial circuits, including a large high performance microprocessor design and a DSP design.