Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Symbolic computation of logic implications for technology-dependent low-power synthesis
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimation of the likelihood of capacitive coupling noise
Proceedings of the 39th annual Design Automation Conference
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Temporofunctional crosstalk noise analysis
Proceedings of the 40th annual Design Automation Conference
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
False-Noise Analysis for Domino Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Eliminating False Positives in Crosstalk Noise Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Delay noise pessimism reduction by logic correlations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst-case noise pulse on the victim net that often leads to false noise violations. In this paper, we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. We propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using ROBDD representations and a newly proposed laterial propagation method. We then show that the problem of finding the worst case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. Initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits and then extend our approach to timed implications. The proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. We demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this paper, underscoring the need for false-noise analysis.