Introduction to algorithms
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
False-noise analysis using logic implications
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Interconnect and noise immunity design for the Pentium 4 processor
Proceedings of the 40th annual Design Automation Conference
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient current-based logic cell model for crosstalk delay analysis
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing analysis with crosstalk is a fixpoint on a complete lattice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an algorithmic framework for fast and accurate static timing analysis considering coupling.With technology scaling to smaller dimensions, the impact of coupling induced delay variations can no longer be ignored. Timing analysis considering coupling is iterative, and can have considerably larger run-times than a single pass approach. We propose two different classes of coupling delay models: heuristic-based coupling model and current source-based coupling model, and present techniques to increase the convergence rate of timing analysis when such coupling models are employed. Our proposed coupling model show promising accuracy improvements compared to SPICE. Experimental results on ISCAS85 benchmarks validates the effectiveness of our efficient iteration scheme. Our iteration algorithm obtained speedups of up to 62.1% using a heuristic coupling model while 2.7× using a current-based coupling model in comparison to traditional approaches.