DAC '96 Proceedings of the 33rd annual Design Automation Conference
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
High-Speed Digital Circuits
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Predicting Performance of Micropipelines Using Charlie Diagrams
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Automated nonlinear Macromodelling of output buffers for high-speed digital applications
Proceedings of the 42nd annual Design Automation Conference
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Current source modeling for power and timing analysis at different supply voltages
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Current source models have emerged as a promising technique for reducing digital cell netlists to a simpler electrical model for use in timing and other applications. The Multiport Current Source Model (MCSM) is one of the most general models in this class, which has been shown to handle multiple electrical effects including multiple-input switching (MIS) events in timing. However, this new model is hampered by two major problems: port characterization runtime and accuracy across a range of complicated cells which are deployed in advanced microprocessor design such as complex combinational cells, muxes, and sequentials. In this paper we demonstrate a significant leap in modeling accuracy and characterization runtime over the MCSM model which effectively eliminates these remaining issues. The quality of the new approach is conclusively demonstrated on a comprehensive 45nm cell library currently in use. The new approach accurately models both complex combinational as well as, for the first time, sequential cells, and puts MCSMs on the path for next generation gate level electrical analysis.