A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
A current source model for CMOS logic cells considering multiple input switching and stack effect
Proceedings of the conference on Design, automation and test in Europe
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RDE-based transistor-level gate simulation for statistical static timing analysis
Proceedings of the 47th Design Automation Conference
Current source modeling in the presence of body bias
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Skew-bounded low swing clock tree optimization
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In nanoscale regime, it is becoming increasingly difficult to model signal shapes using simple ramp-like waveforms due to various noise coupling effects. We present an accurate waveform independent gate(WiM) model without any assumption of signal waveforms. Our model can be applied to arbitrary gate inputs while maintaining excellent near- SPICE accuracy. The application of the proposed gate modeling technique is demonstrated under the context of the gate-level timing simulation.