Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power reduced swing global clocking methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
Integrated Clock Mesh Synthesis With Incremental Register Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper introduces a methodology that optimizes the performance of a low swing clock tree under a skew bound. Low-swing clock trees are preferred for a reduction in the clock switching power, with an expected trade-off in clock slew and skew. In this paper, a heuristic optimization process is introduced that keeps the clock skew under the same skew budget of the originating full-swing clock tree. In this low swing clock optimization, the low power consumption property is preserved. The effect of slew on the logic timing, which is naturally degraded due to low-swing operation, is analyzed within timing slack of some paths in order to highlight the effectiveness of the low swing clock trees in lowering power consumption with limited impact on timing constraints. The experiments performed with the 4 largest ISCAS'89 benchmark circuits operating at 500~MHz, 90~nm technology and 4 different Vdd levels show that the optimized low swing clock tree can achieve an average of upto 11.0% reduction in the power consumption with no more than a skew degradation of 0.5% of the clock period (i.e. within the practical skew budget).