A low-power reduced swing global clocking methodology

Authors:
Farhad Haj Ali Asgari;Manoj Sachdev
Affiliations:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1, Canada;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 5
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Abstract

In this brief, we investigate the potential of reduced swing clock networks for low-power applications. We designed and laid out a full swing conventional and a reduced swing H-tree clock distribution network in 0.13-µm CMOS technology operating at 500 MHz. In the reduced swing clock network, the swing was reduced in the global clock distribution network and was restored to the full swing in the local clock distribution domains. The post-layout simulation results of this research shows that a power saving of 22% under nominal operating condition is feasible.