Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Authors:
Sherif A. Tawfik;Volkan Kursun
Affiliations:
University of Wisconsin-Madison;University of Wisconsin-Madison
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

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Abstract

A methodology based on supply voltage and frequency scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a scaled supply voltage and frequency. The optimum supply voltage that minimizes clock skew is 44% less than the nominal supply voltage in a 0.18μm CMOS technology. Combined frequency multiplier and level converter circuits are utilized at the leaves of the clock tree for restoring the standard full voltage swing clock signal with the higher target clock frequency in order to maintain the performance of the system. A novel dual-threshold-voltage frequency doubler with voltage level conversion capability, suppressed temperature fluctuations sensitivity, and low power consumption characteristics is presented. The temperature fluctuations induced skew and power consumption of the proposed dual-VDD/dual-frequency clock distribution network are reduced by up to 80% and 76%, respectively, as compared to a standard distribution network operating at the nominal supply voltage with the target system clock frequency.