Energy efficient swing signal generation circuits for clock distribution networks

Authors:
Khader Mohammad;Bao Liu;Sos Agaian
Affiliations:
Electrical and Computer Engineering Department, University of Texas at San Antonio, San Antonio, TX;Electrical and Computer Engineering Department, University of Texas at San Antonio, San Antonio, TX;Electrical and Computer Engineering Department, University of Texas at San Antonio, San Antonio, TX
Venue:
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
Year:
2009

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Abstract

We propose Reduced Voltage Swing (RVS) signaling (by elevating the logic 0 voltage) as opposed to Low Voltage Swing (LVS) signaling (which reduces the logic 1 voltage). We propose an inverter which generates RVS signals, and an extension with programmable logic for adjusted logic 0 voltage. The proposed RVS scheme achieves reduced active power consumption, minimum performance degradation and minimum area overhead (without extra power supply network and a minimum number of extra transistors). Application of multi-threshold voltage design further alleviates compromises on noise margin and leakage. Experimental results based on SPICE simulation show that RVS clocking achieves an average of 37% active power consumption reduction, 8% performance degradation.