Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Design Challenges of Technology Scaling
IEEE Micro
VLSI Architecture: Past, Present, and Future
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Performance of interconnection rip-up and reroute strategies
DAC '81 Proceedings of the 18th Design Automation Conference
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
Package level interconnect options
Proceedings of the 2005 international workshop on System level interconnect prediction
Explaining the gap between ASIC and custom power: a custom perspective
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Constant impedance scaling paradigm for interconnect synthesis
Proceedings of the 2006 international workshop on System-level interconnect prediction
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
Proceedings of the 2006 international workshop on System-level interconnect prediction
An automated design flow for 3D microarchitecture evaluation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
A case for a complexity-effective, width-partitioned microarchitecture
ACM Transactions on Architecture and Code Optimization (TACO)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interconnect design considerations for large NUCA caches
Proceedings of the 34th annual international symposium on Computer architecture
An analysis of timing violations due to spatially distributed thermal effects in global wires
Proceedings of the 44th annual Design Automation Conference
CAD implications of new interconnect technologies
Proceedings of the 44th annual Design Automation Conference
Interconnect and communication synthesis for distributed register-file microarchitecture
Proceedings of the 44th annual Design Automation Conference
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
IntSim: A CAD tool for optimization of multilevel interconnect networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Soft-edge flip-flops for improved timing yield: design and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Broadcast filtering-aware task assignment techniques for low-power MPSoCs
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Exploring power management in multi-core systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Asynchronous control of modules activity in integrated systems for reducing peak temperatures
Integration, the VLSI Journal
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Journal of Supercomputing
Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling of on-chip bus switching current and its impact on noise in power supply grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
High performance on-chip differential signaling using passive compensation for global communication
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Broadcast filtering: Snoop energy reduction in shared bus-based low-power MPSoCs
Journal of Systems Architecture: the EUROMICRO Journal
Low Power Gated Clock Tree Driven Placement
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Better than optimum?: register reduction using idle pipelined functional units
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-delay optimization in VLSI microprocessors by wire spacing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Prediction of high-performance on-chip global interconnection
Proceedings of the 11th international workshop on System level interconnect prediction
Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Energy efficient swing signal generation circuits for clock distribution networks
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
Impact of local interconnects on timing and power in a high performance microprocessor
Proceedings of the 19th international symposium on Physical design
Interconnect power and delay optimization by dynamic programming in gridded design rules
Proceedings of the 19th international symposium on Physical design
A scalable organization for distributed directories
Journal of Systems Architecture: the EUROMICRO Journal
HiPC'07 Proceedings of the 14th international conference on High performance computing
The SKB: a semi-completely-connected bus for on-chip systems
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Workload-adaptive process tuning strategy for power-efficient multi-core processors
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Clock network design for ultra-low power applications
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A pareto-algebraic framework for signal power optimization in global routing
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
Journal of Systems Architecture: the EUROMICRO Journal
PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks
Proceedings of the Conference on Design, Automation and Test in Europe
Interconnect bundle sizing under discrete design rules
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A global interconnect reduction technique during high level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
Microprocessors & Microsystems
Enabling quality-of-service in nanophotonic network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Wafer-level package interconnect options
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On-chip interconnect analysis of performance and energy metrics under different design goals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire topology optimization for low power CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
F2BFLY: an on-chip free-space optical network with wavelength-switching
Proceedings of the international conference on Supercomputing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Analog Integrated Circuits and Signal Processing
Energy-efficient cache coherence protocol for NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design
Proceedings of the 48th Design Automation Conference
A framework for architecture-level exploration of 3-D FPGA platforms
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Using well-solvable quadratic assignment problems for VLSI interconnect applications
Discrete Applied Mathematics
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
The complexity of VLSI power-delay optimization by interconnect resizing
Journal of Combinatorial Optimization
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era
Proceedings of the International Workshop on System Level Interconnect Prediction
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
The optimal fan-out of clock network for power minimization by adaptive gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-hop communications on wireless network-on-chip using optimized phased-array antennas
Computers and Electrical Engineering
DESC: energy-efficient data exchange using synchronized counters
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Optimizing effective interconnect capacitance for FPGA power reduction
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
A novel 3-D FPGA architecture targeting communication intensive applications
Journal of Systems Architecture: the EUROMICRO Journal
DP&TB: a coherence filtering protocol for many-core chip multiprocessors
The Journal of Supercomputing
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Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50% of the dynamic power. Over 90% of the interconnect power is consumed by only 10% of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router's algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The power-aware router algorithm was tested on synthesized blocks, demonstrating average saving of 14% in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.