Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic accelerators

Authors:
Tom English;Emanuel Popovici
Affiliations:
University College Cork, Ireland;University College Cork, Ireland
Venue:
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Year:
2011

Citing 11
Cited 0

A Scalable Dual-Field Elliptic Curve Cryptographic Processor

IEEE Transactions on Computers
Interconnect-power dissipation in a microprocessor

Proceedings of the 2004 international workshop on System level interconnect prediction
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods

Proceedings of the 2004 international workshop on System level interconnect prediction
Design of a scalable RSA and ECC crypto-processor

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations

CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Hardware architectures for the Tate pairing over GF(2m)

Computers and Electrical Engineering
Bringing NoCs to 65 nm

IEEE Micro
FPGA and ASIC implementations of the ηT pairing in characteristic three

Computers and Electrical Engineering
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration

Proceedings of the Conference on Design, Automation and Test in Europe
Network-on-Chip interconnect for pairing-based cryptographic IP cores

Journal of Systems Architecture: the EUROMICRO Journal
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper introduces Interconnect Physical Analyser (IPAA) - a tool for the analysis and optimisation of SoC/NoC toplevel interconnect. IPAA extracts information from the IC router and power analysis tool after implementation. Combining information from both sources, the tool performs a wirelength-driven power analysis of toplevel interconnect in the design. A range of statistics for toplevel interconnect is reported and a set of plots is produced. Multiple designs can be analysed simultaneously, enabling comparison and optimisation. The tool is applied to the design of scalable, efficient bus-replacement Network-on-Chip interconnect for Public Key Cryptographic accelerators. IPAA analyses the physical effects of scaling the cryptographic accelerator's floorplan, the number of cores and the cryptographic wordlength. The tool's plots and reports highlight the efficiency and scalability of the bus replacement Network-on-Chip and help guide the optimisation of the design.