Hardware architectures for the Tate pairing over GF(2m)

Authors:
Maurice Keller;Robert Ronan;William Marnane;Colin Murphy
Affiliations:
Department of Electrical and Electronic Engineering, University College Cork, Cork City, Ireland;Department of Electrical and Electronic Engineering, University College Cork, Cork City, Ireland;Department of Electrical and Electronic Engineering, University College Cork, Cork City, Ireland;Department of Electrical and Electronic Engineering, University College Cork, Cork City, Ireland
Venue:
Computers and Electrical Engineering
Year:
2007

Citing 9
Cited 6

Low-Energy Digit-Serial/Parallel Finite Field Multipliers

Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Efficient Algorithms for Pairing-Based Cryptosystems

CRYPTO '02 Proceedings of the 22nd Annual International Cryptology Conference on Advances in Cryptology
Implementing the Tate Pairing

ANTS-V Proceedings of the 5th International Symposium on Algorithmic Number Theory
From Euclid's GCD to Montgomery Multiplication to the Great Divide

From Euclid's GCD to Montgomery Multiplication to the Great Divide
Parallel Hardware Architectures for the Cryptographic Tate Pairing

ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
An Embedded Processor for a Pairing-Based Cryptosystem

ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
Software implementation of Tate pairing over GF(2m)

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Hardware acceleration of the tate pairing in characteristic three

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Efficient hardware for the tate pairing calculation in characteristic three

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems

A Comparison between Hardware Accelerators for the Modified Tate Pairing over $\mathbb{F}_{2^m}$ and $\mathbb{F}_{3^m}$

Pairing '08 Proceedings of the 2nd international conference on Pairing-Based Cryptography
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers

CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves

CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
FPGA and ASIC implementations of the ηT pairing in characteristic three

Computers and Electrical Engineering
Network-on-Chip interconnect for pairing-based cryptographic IP cores

Journal of Systems Architecture: the EUROMICRO Journal
Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic accelerators

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design parameters are presented.